US Patent Issued to TAIWAN SEMICONDUCTOR MANUFACTURING, NATIONAL TSING HUA UNIVERSITY on Oct. 20 for "Memory device and operating method thereof" (Taiwanese Inventors)

Posted On: 2026-10-21

ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,703, issued on Oct. 20, was assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. (Hsinchu, Taiwan) and NATIONAL TSING HUA UNIVERSITY ... Read More

US Patent Issued to Micron Technology on Oct. 20 for "Recycled fine granularity counter-based RAS chain" (Idaho Inventors)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,704, issued on Oct. 20, was assigned to Micron Technology Inc. (Boise, Idaho). "Recycled fine granularity counter-based RAS chain" was inve... Read More

US Patent Issued to QUALCOMM on Oct. 20 for "Memory mirror sequencing for reduced latency in memory patching" (Indian Inventors)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,705, issued on Oct. 20, was assigned to QUALCOMM Inc. (San Diego). "Memory mirror sequencing for reduced latency in memory patching" was in... Read More

US Patent Issued to MimirIP on Oct. 20 for "Memory, memory system, operation method of the memory, and operation of the memory system" (South Korean Inventors)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,706, issued on Oct. 20, was assigned to MimirIP LLC (Dallas). "Memory, memory system, operation method of the memory, and operation of the ... Read More

US Patent Issued to Micron Technology on Oct. 20 for "Bit inversion techniques for memory system repair indications" (German Inventors)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,707, issued on Oct. 20, was assigned to Micron Technology Inc. (Boise, Idaho). "Bit inversion techniques for memory system repair indicatio... Read More

US Patent Issued to Canon on Oct. 20 for "Semiconductor device and apparatus" (Japanese Inventor)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,708, issued on Oct. 20, was assigned to Canon K.K. (Tokyo). "Semiconductor device and apparatus" was invented by Koichi Iwao (Tokyo). Acco... Read More

US Patent Issued to Advanced Micro Devices on Oct. 20 for "Link stress pattern to ensure command address bus integrity" (California Inventor)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,709, issued on Oct. 20, was assigned to Advanced Micro Devices Inc. (Santa Clara, Calif.). "Link stress pattern to ensure command address b... Read More

US Patent Issued to SAMSUNG ELECTRONICS on Oct. 20 for "Method of error correction code (ECC) decoding and memory system performing the same" (South Korean Inventors)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,710, issued on Oct. 20, was assigned to SAMSUNG ELECTRONICS Co. Ltd. (Suwon-si, South Korea). "Method of error correction code (ECC) decodi... Read More

US Patent Issued to Micron Technology on Oct. 20 for "Logic-based defective memory component screening" (Singaporean, American Inventors)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,711, issued on Oct. 20, was assigned to Micron Technology Inc. (Boise, Idaho). "Logic-based defective memory component screening" was inven... Read More

US Patent Issued to ARRAPOI on Oct. 20 for "Unique input-response relationships from parameter sets having a reduced scale and a reduced number of variables" (California Inventor)

Posted On: 2026-10-21

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ALEXANDRIA, Va., Oct. 21 -- United States Patent no. 12,770,712, issued on Oct. 20, was assigned to ARRAPOI INC. (Redwood City, Calif.). "Unique input-response relationships from parameter sets havin... Read More

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US Patent Issued to TAIWAN SEMICONDUCTOR MANUFACTURING, NATIONAL TSING HUA UNIVERSITY on Oct. 20 for "Memory device and operating method thereof" (Taiwanese Inventors)

US Patent Issued to Micron Technology on Oct. 20 for "Recycled fine granularity counter-based RAS chain" (Idaho Inventors)

US Patent Issued to QUALCOMM on Oct. 20 for "Memory mirror sequencing for reduced latency in memory patching" (Indian Inventors)

US Patent Issued to MimirIP on Oct. 20 for "Memory, memory system, operation method of the memory, and operation of the memory system" (South Korean Inventors)

US Patent Issued to Micron Technology on Oct. 20 for "Bit inversion techniques for memory system repair indications" (German Inventors)

US Patent Issued to Canon on Oct. 20 for "Semiconductor device and apparatus" (Japanese Inventor)

US Patent Issued to Advanced Micro Devices on Oct. 20 for "Link stress pattern to ensure command address bus integrity" (California Inventor)

US Patent Issued to SAMSUNG ELECTRONICS on Oct. 20 for "Method of error correction code (ECC) decoding and memory system performing the same" (South Korean Inventors)

US Patent Issued to Micron Technology on Oct. 20 for "Logic-based defective memory component screening" (Singaporean, American Inventors)

US Patent Issued to ARRAPOI on Oct. 20 for "Unique input-response relationships from parameter sets having a reduced scale and a reduced number of variables" (California Inventor)